NI PXIe-4142

Core Technical & Performance Specifications

1. Channel Configuration: Four fully independent, electrically isolated SMU measurement channels per single-width PXI Express module
2. Voltage Source & Measurement Range Per Channel: ±24 V DC full-scale operating range
3. Current Source & Measurement Range Per Channel: ±150 mA DC full-scale operating range
4. DC Power Rating Per Individual Channel: Maximum 3.6 W DC sourcing power; maximum 3.6 W DC sinking power (four-quadrant power operation capability)
5. Low-Level Current Measurement Sensitivity: 100 pA minimum detectable current resolution
6. Sampling & Update Rate Performance
   • Maximum Analog Measurement Sampling Rate: 600 kS/s per channel
   • Maximum DC Source Output Update Rate: 100 kS/s per channel
7. Transient Response Control: Fixed predefined transient response speed profiles (Slow, Medium, Fast); no user-customizable SourceAdapt transient response tuning functionality
8. Four-Wire Remote Sensing: Integrated remote sense terminal connections on each channel front-panel connector to eliminate voltage drop measurement errors across test fixture wiring resistance
9. Onboard Measurement Buffer: Dedicated FIFO data acquisition memory buffer per individual channel for high-speed streaming measurement data capture
10. Physical & Environmental Specifications
    • Form Factor: Single-width 3U PXI Express module
    • Operating Ambient Temperature Range: 0 °C to 55 °C
    • Relative Humidity Operating Rating: 10%–90% non-condensing
    • Maximum Operating Altitude: 2000 m above sea level

Key Functional Features

1. Four fully independent four-quadrant SMU channels integrated within a compact single-width PXI Express module, delivering industry-leading high channel density to minimize total chassis slot count requirements for multi-device parallel characterization test systems
2. Simultaneous concurrent voltage/current sourcing and precision voltage/current measurement operation on every channel; eliminates sequential source-measure operation latency for high-throughput automated semiconductor production test workflows
3. Integrated four-wire remote sense circuitry per channel to fully compensate for parasitic voltage drop errors introduced by test fixture cabling, contact resistance, and probe station needle contact resistance during low-impedance DUT (device under test) characterization measurements
4. Ultra-high sensitivity low-leakage current measurement capability down to 100 pA resolution, optimized for characterizing ultra-low power semiconductor devices, MEMS transducers, photodiodes, and thin-film transistor (TFT) microelectronic components
5. Hardware-timed synchronized measurement triggering architecture fully compatible with PXI Express chassis backplane 10 MHz reference clock and star trigger bus; enables precise nanosecond-scale time-aligned multi-channel, multi-module SMU test sequencing
6. Onboard dedicated FPGA digital control logic to offload repetitive source-measure test sequencing operations from host control PC CPU, drastically reducing host PC communication bus bandwidth load and improving overall test system throughput speed
7. Comprehensive NI-DCPower instrument driver software support, fully compatible with LabVIEW, LabWindows/CVI, Python, C#, C++, and TestStand automated test sequencing software environments
8. Built-in hardware overvoltage, overcurrent, overpower, and reverse polarity protection circuits on every independent SMU channel to prevent permanent DUT device damage and module internal component burnout during automated unattended production test operations

Working Principle

1. Voltage & Current Sourcing Signal Path Working Principle
   • Host control PC transmits user-defined target voltage and current source setpoint values over the PXI Express high-speed serial backplane bus to the module’s onboard industrial FPGA control logic chip
   • FPGA logic processes setpoint commands and generates precision analog control signals to drive dual closed-loop voltage and current regulator power amplifier circuits for each independent SMU channel
   • Dual closed-loop regulation architecture enables seamless automatic transition between constant voltage (CV) sourcing mode and constant current (CC) sourcing mode on every channel without external hardware switching relays
2. Precision Measurement Signal Path Working Principle
   • DUT voltage and current signals are simultaneously sampled via two separate high-precision analog-to-digital converter (ADC) circuits per channel, operating at maximum 600 kS/s sampling rate
   • Four-wire remote sense input terminals route direct DUT voltage measurement signals to dedicated high-impedance ADC input amplifiers, completely bypassing parasitic voltage drop across front-panel output cabling and test fixture contact resistance
   • Low-noise transimpedance amplifier preconditioning circuitry processes ultra-low magnitude DUT current signals down to 100 pA level, amplifying microamp and picoamp range current signals to measurable voltage levels for high-resolution ADC conversion
3. Four-Quadrant Power Operation Working Principle
   • Each channel’s dual regulator power amplifier circuit architecture supports bidirectional power flow operation: sourcing positive/negative DC power to the DUT device, and sinking (absorbing) positive/negative DC power from the DUT device into the module’s internal power dissipation load circuit
   • Four-quadrant operation enables accurate characterization of active semiconductor devices capable of both consuming and generating electrical power (photovoltaic diodes, rechargeable micro-batteries, piezoelectric MEMS transducers)
4. Onboard FPGA Control & Trigger Synchronization Working Principle
   • High-speed FPGA logic executes real-time closed-loop voltage/current regulation, multi-channel measurement sampling sequencing, hardware trigger signal generation, and onboard FIFO data buffer storage operations independent of host PC CPU processing cycles
   • Module front-panel trigger I/O terminals and PXI Express backplane trigger bus interface receive synchronized timing reference signals from chassis 10 MHz clock and star trigger bus hardware; FPGA logic aligns all channel source-measure sampling events to the global chassis synchronous timing reference for precise multi-module time alignment
5. Hardware Fault Protection Working Principle
   • Independent analog fault monitoring circuits continuously sample each channel’s output voltage, output current, and total power dissipation values in real time
   • If sampled measurement values exceed user-programmable overvoltage, overcurrent, or overpower fault threshold limits, fault monitoring hardware immediately triggers a rapid channel output disconnect sequence, cutting off all source power delivery to the DUT device to prevent component burnout or permanent DUT damage

Structure & Material Composition

1. Module Main Multi-Layer PCB: UL94 V-0 flame retardant FR4 high-frequency printed circuit board with isolated analog and digital ground plane layers to minimize digital switching noise coupling into low-level precision analog measurement signal traces
2. Precision Analog Circuit Components: Low-noise JFET input operational amplifier ICs, high-stability thin-film precision voltage divider resistors, low-leakage ceramic and polypropylene signal decoupling capacitors, matched transimpedance amplifier feedback resistor networks for picoamp current measurement
3. Power Regulation Amplifier Hardware: High-efficiency bidirectional power MOSFET amplifier arrays, low equivalent series resistance (ESR) power bulk capacitors, high-temperature surface-mount power inductors, thermal dissipation copper PCB pour heat sink regions for power amplifier heat extraction
4. Digital Control Logic Hardware: Industrial-grade Xilinx FPGA chip, high-speed PXI Express serial interface physical layer transceiver ICs, low-jitter crystal oscillator timing reference circuits, non-volatile EEPROM memory for user calibration coefficient storage
5. Front Panel Assembly: Die-cast aluminum alloy matte black powder-coated front panel with engraved channel number identification text, gold-plated multi-pin signal connector terminals for SMU output force lines and four-wire remote sense lines, front-panel trigger input/output BNC coaxial signal connectors, stainless steel retention screw hardware for chassis slot mounting
6. EMC Shielding Components: Formed tin-plated steel internal analog/digital compartment shielding cans to isolate high-speed digital FPGA switching noise from low-noise precision analog measurement circuitry

Installation Mandatory Requirements

1. Mechanical Module Installation Rules
   • Insert module exclusively when target PXI Express chassis main AC power supply is fully disconnected from mains wall socket to avoid backplane bus short-circuit damage and module component electrostatic discharge burnout
   • Slide module fully into selected chassis peripheral slot until front panel forms flush contact with chassis slot faceplate; evenly tighten left and right front-panel retention screws to ensure full electrical contact between module gold-plated edge connector and chassis backplane slot contacts
   • Install nylon plastic blank filler panels on all unused empty chassis slots to preserve uniform forced-air cooling internal airflow distribution and maintain chassis electromagnetic EMC shielding integrity
2. DUT Test Fixture Wiring Installation Rules
   • Implement separate dedicated shielded coaxial wiring bundles for each channel’s force output lines and four-wire remote sense measurement lines; physically separate high-current force wiring and high-impedance low-level sense wiring to eliminate capacitive and inductive signal crosstalk interference between channels
   • Connect four-wire remote sense terminals directly to the physical DUT device contact points (probe station needle tips, component device package pins) to fully eliminate parasitic wiring resistance voltage drop measurement errors; avoid connecting sense terminals to distant test fixture terminal block points
   • Install external high-precision current-limiting series resistors on all channel force output lines when characterizing ultra-fragile microelectronic DUT devices to provide secondary overcurrent fault protection backup in addition to the module’s onboard hardware fault protection circuits
3. PXI Express Chassis Synchronization Installation Rules
   • Ensure chassis backplane 10 MHz low-jitter reference clock and star trigger bus hardware are enabled and functional; route inter-module synchronization trigger signals via chassis internal backplane trigger bus rather than external front-panel BNC trigger cables to minimize trigger signal propagation delay jitter
4. Software Driver Installation Rules
   • Install complete NI-DCPower instrument driver software suite matching the host operating system version prior to chassis power-up and module hardware detection
   • Launch NI MAX measurement automation configuration software after chassis power-on to execute automated module hardware discovery, run full onboard hardware self-test diagnostic routines, verify multi-channel SMU analog measurement calibration integrity, and allocate system hardware memory and interrupt resources to the module
   • Configure channel-specific fault protection threshold limits (overvoltage, overcurrent, overpower), constant voltage/current source mode operating parameters, and four-wire remote sense measurement enable/disable settings within NI MAX prior to deploying custom automated semiconductor characterization test application code

Strict Usage Precautions

1. Precision Analog Measurement Noise Precautions
   • Operate module exclusively inside properly EMC-shielded PXI Express chassis with all empty slots fitted with plastic filler panels; unshielded open chassis operation allows external industrial electromagnetic interference noise to corrupt ultra-low-level picoamp and nanoamp current measurement data, introducing severe measurement inaccuracies
   • Route all DUT test fixture shielded signal wiring away from high-voltage AC mains power cables, industrial motor drive wiring, relay control wiring, and switching power supply wiring to eliminate inductive and capacitive EMI noise coupling into precision analog measurement signal lines
2. Thermal Power Dissipation Precautions
   • Maintain chassis cooling fan operation at HIGH fixed speed mode during continuous full-load four-channel simultaneous maximum power sourcing/sinking operation; sustained high power dissipation across all four channels generates significant internal heat load which requires maximum forced-air cooling airflow volume to prevent module internal power amplifier component thermal throttling and over-temperature shutdown fault events
   • Avoid stacking multiple high-power SMU modules in adjacent chassis peripheral slots without maximum cooling fan speed enabled; concentrated localized heat buildup between adjacent power-heavy modules creates uneven thermal distribution and accelerates internal component aging and drift of precision analog measurement calibration coefficients
3. Electrical DUT Protection Precautions
   • Always program conservative overvoltage, overcurrent, and overpower fault threshold limits matching the absolute maximum rated electrical operating parameters of the DUT semiconductor device under test prior to executing automated unattended test sequencing operations; overly lenient fault threshold limits eliminate critical hardware fault protection against accidental DUT device burnout
   • When characterizing photovoltaic devices, rechargeable micro-batteries, and power-generating piezoelectric MEMS transducers capable of sinking reverse power into the SMU channel output terminals, strictly adhere to each channel’s maximum 3.6 W power sinking rating to avoid exceeding internal power dissipation load thermal limits